This application claims priority under 35 USC §119 to Korean Patent Application No. 2005-78583, filed on Aug. 26, 2005 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to generating a back-bias voltage, and more particularly, to generating a back-bias voltage with high temperature sensitivity for compensating characteristics of a semiconductor memory device that vary with temperature.
2. Description of the Related Art
In general, a semiconductor memory device, particularly a DRAM (dynamic random access memory) device, applies a back-bias voltage (VBB) to p-type wells. Such P-type wells each have formed therein an NMOS (N-channel metal oxide semiconductor) transistor as a cell transistor of the DRAM device.
The applied VBB may improve a refresh characteristic of the DRAM device by increasing a threshold voltage of the cell transistor (consequently decreasing a leakage current). In addition, the applied VBB may stabilize circuit operation by decreasing a change of the threshold voltage of the cell transistor.
FIG. 1 shows a block diagram of a conventional back-bias voltage (VBB) generating circuit. Referring to FIG. 1, the conventional VBB generating circuit includes a VBB detector circuit 10, an oscillator 20, and a charge pumping circuit 30. The VBB detector 10 detects a level of the VBB voltage generated by the charge pumping circuit 30. The VBB detector 10 generates an enable signal EN that is provided to the oscillator 20.
The enable signal EN is activated to a logic high state from a logic low state by the VBB detector when the absolute value of the VBB voltage is less than a monitoring level, and deactivates the enable signal EN other-wise. The oscillator 20 generates an oscillating signal OS when the enable signal EN is activated. The charging pumping circuit 30 pumps charge to a substrate (i.e., a P-well for example) of the memory device in response to the generated oscillating signal OS.
FIG. 2 shows a circuit diagram of the conventional VBB detector 10 in the VBB generating circuit of FIG. 1. Referring to FIG. 2, the conventional VBB detector 10 includes a voltage divider 12, a first CMOS inverter 14, and a second COMS inverter 16.
The voltage divider 12 outputs a divided voltage having a level that is divided by a ratio of a turn-on resistance of a first PMOS (P-channel metal oxide semiconductor) transistor PM11 to a turn-on resistance of a second PMOS transistor PM12. The turn-on resistance of the first PMOS transistor PM11 is substantially constant since a gate of the first PMOS transistor PM11 is coupled to ground. On the other hand, the turn-on resistance of the second PMOS transistor PM12 varies depending upon the voltage level of VBB that is applied to a gate of the second PMOS transistor PM12.
Thus, the divided voltage Vdiv from the voltage divider 12 varies with the change of the turn-on resistance of the second PMOS transistor PM12. The level change of the divided voltage Vdiv is detected by the first CMOS inverter 14 for being converted into a pulse signal having a variable pulse width. The pulse signal from the first CMOS inverter 14 is converted to the enable signal EN having a full CMOS level by the second inverter 16. The enable signal EN output from the second inverter 16 is applied to the oscillator 20.
The oscillator 20 is enabled to generate an oscillating signal OS when the enable signal EN is activated. The charge pumping circuit 30 pumps charge to a substrate in response to the generated oscillating signal OS to increase the absolute value of VBB. When the absolute value of VBB is no longer less than the absolute value of the monitoring level, the enable signal EN from the detecting circuit 10 is deactivated from the logic high state to the logic low state. Accordingly, the oscillator 20 and the charge pumping circuit 30 are disabled in response to the deactivated enable signal EN. The VBB level is constantly monitored in this manner such that the VBB level is maintained within a predetermined range.
FIG. 3 shows waveforms of the enable signal EN generated by the conventional VBB detector according to temperature variation. Referring to FIG. 3, the absolute value of the monitoring level of the conventional VBB detector 10 is decreased with the temperature. In addition, such a change of the monitoring level is very insignificant.
Accordingly, the boosting margin characteristic of a word line driving voltage for the DRAM memory device remains deteriorated at low temperatures. In addition, the refresh characteristic for the DRAM memory device remains deteriorated at high temperatures.